ASIC Senior I Engineer [Code: ASIP-03]

Job Description:

  • Candidate will develop thorough understanding of system level design specifications.
  • Candidate will work on RTL Coding/Synthesis of digital part of Mixed Signal IPs.
  • Candidate will develop behavioral models for the analog parts of Mixed Signal IPs.
  • Candidate will develop advanced verification environment and test-bench components.
  • Candidate should work with the Mixed Signal team on the co-simulation and verification of the IPs.
  • Candidate will be responsible of hardware verification of the digital module using cutting edge FPGA
    kits.
  • Candidate should meet strict quality and schedule requirements.

Qualifications:

  • B.Sc./M.Sc. in Electronics Engineering.
  • 4-9 Years of experience in VLSI Digital Design/Verification.
  • Strong knowledge of Verilog RTL design/simulation.
  • Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
  • Familiarity with System Verilog, RTL/gate verification techniques is a plus.
  • Oral and written fluency in English.
  • Knowledge of Unix/Linux operating system is a plus.
  • Knowledge of shell scripting/programming languages is a plus.

Address

5 Mostafa Refaat St, First Floor,
Sheraton Buildings, Square 1135,
Heliopolis, Cairo 11361, Egypt.
Phone: (+2) 02.22.69.24.69
Fax: (+2) 02.22.69.25.35
Website: http://mipex.net
Email: info@mipex.net