ASIC Junior Engineer [Code: ASIP-01]

Job Description:

  • Candidate will develop thorough understanding of system level design specifications.
  • Candidate will work on RTL Coding/Synthesis of digital part of Mixed Signal IPs.
  • Candidate will develop behavioral models for the analog parts of Mixed Signal IPs.
  • Candidate will develop advanced verification environment and test-bench components.
  • Candidate should work with the Mixed Signal team on the co-simulation and verification of the IPs.
  • Candidate will be responsible of hardware verification of the digital module using cutting edge FPGA


  • B.Sc./M.Sc. in Electronics Engineering.
  • 0-4 Years of experience in VLSI Digital Design/Verification.
  • Strong knowledge of Verilog RTL design/simulation.
  • Knowledge of ASIC/FPGA design flows including RTL Synthesis, Place and Route, and Timing Sign-off.
  • Familiarity with System Verilog, RTL/gate verification techniques is a plus.
  • Oral and written fluency in English.
  • Knowledge of Unix/Linux operating system is a plus.
  • Knowledge of shell scripting/programming languages is a plus.


5 Mostafa Refaat St, First Floor,
Sheraton Buildings, Square 1135,
Heliopolis, Cairo 11361, Egypt.
Phone: (+2)
Fax: (+2)